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Original Authors: Ferenc Fodor, IMEC
Edited by Cyth Systems
The Challenge
Performing die tests prior to stacking 3D ICs to achieve sufficient compound stack yield by probing the interconnect micro bumps for pre-bond test access.
The Solution
Building a unique fully automatic system to characterize prototype probe cards for large-array, fine-pitch microbumps on our advanced test wafers using NI PXI instruments and the Semiconductor Test System (STS).
3D-Stacked ICs to Conquer the World
The research on 3D stacked IC (3D-SIC) technology has advanced to the point that virtually all semiconductor companies have now released or announced 3D-SIC products, or are developing such products in stealth mode. In 3D-SIC packages, multiple chip dies are stacked vertically, which results in a dense integration, possibly involving heterogeneous technologies, in an ultra-small footprint with considerable benefits for performance, power, and cost.
One challenge in stacking ICs is to retain a high compound yield and not include faulty dies. This requires testing the dies before stacking them, for example, through the interconnect microbumps. But engineers have long considered it impossible to probe these microbumps because the arrays are too large (≥1,000) and the pitches too small (≤40 µm). We developed a solution: a fully automated system to characterize prototype probe cards for large-array, fine-pitch microbumps on advanced test wafers using the Semiconductor Test System (STS) from NI.
State-of-the-art microbumps have the following specifications (see Figure 2): Landing bump: Cu, diameter 25 µm Top bump: Cu/Ni/Sn, diameter 15 µm
Imec is the world-leading R&D center for nano-electronics and digital technology, headquartered near Leuven, Belgium, and with 3,500 researchers. We use state-of-the-art infrastructure, including our 200 mm and 300 mm wafer fabs, to perform research for a multitude of industries, including eight of the top 10 semiconductor companies. Our research program on 3D system integration is an imec Industrial Affiliation Program in which our own staff work alongside engineers from our industrial partners, key suppliers, and leading academic partners toward radical innovation and pre-competitive development.
Imec has contributed to the field of 3D-SICs for over a decade through research into:
Through-silicon vias (TSVs) that allow making electrical connections to a silicon substrate’s back side
Dense microbump interconnects between stacked dies
Wafer thinning, bonding and debonding
Various (die-to-die, die-to-wafer, and wafer-to-wafer) stacking approaches We have also studied architecture, design, manufacturing, test, reliability, and thermal aspects of 3D-SICs through simulations and actual measurements on numerous test chips.
Challenges in Probing 3D-SIC Microbumps
Due to its many high-precision steps, semiconductor manufacturing is prone to defects. Therefore, every IC needs to undergo electrical tests to weed out defective parts and guarantee product quality. This is also true for 3D-SICs, which typically contain complex die designs in advanced technology nodes, and therefore need to be tested through today’s most advanced test and design-for-test approaches.
In addition, a number of test challenges are unique to the 3D-SIC stacking process itself. One of these is testing dies prior to stacking, which is essential to obtain acceptable compound stack yields and not lose good dies in a stack with one faulty die.
The non-bottom dies of the stacks have their functional access exclusively through large arrays of fine-pitch microbumps, which are too dense for conventional probe technology. A common approach to obtain pre-bond test access is to equip these dies with dedicated pre-bond probe pads [1][2][3]. Unfortunately, this approach comes with drawbacks such as an increased silicon area and test application time, and a reduced interconnect performance. To avoid the many drawbacks associated with dedicated pre-bond probe pads, imec and key partners set out to enable probing directly on the microbumps, a task previously thought impossible.
State-of-the-art microbumps have the following specifications (see Figure 2):
Landing bump: Cu, diameter 25 µm
Top bump: Cu/Ni/Sn, diameter 15 µm
Demonstrating Feasibility of Microbump Probing With the Help of NI
To address these challenges, we teamed up with leading probe card supplier Cascade Microtech (Oregon, USA), who provided us with prototypes of their advanced Pyramid® Rocking Beam Interposer (RBI) probe cards (see Figure 4a). These probe cards contain an IC-design-specific probe core which includes a thin film with MEMS-type probe tips (see Figure 4b). Cascade’s high-density probe cores support >1,200 core I/Os, which is sufficient for WIO1. The RBI probe tips require less than 1 gf/tip to make proper electrical contact. The heel of the tip makes physical contact to the wafer (see Figure 4c), such that the probe mark is typically only 6 µm × 1 µm (see Figure 7).
To prove the feasibility of microbump probing with these probe cards, we built a unique full-automatic test system (see Figure 5) consisting of (1) a dual CM300 probe station from Cascade Microtech (Germany), (2) a hard-docking STS test head with PXI test instruments from NI, (3) a test head manipulator from Reid-Ashman (Utah, USA), and (4) test program and data analysis software based on LabVIEW and developed at imec.
The NI STS test head is a T2 model that contains two PXI racks with test instruments. Rack 1 holds instruments for parametric and functional tests. Rack 2 is dedicated to microbump probing. It contains a PXI-4072 digital multimeter (DMM) connected to an ultra-wide switch matrix (SMX1–9) consisting of nine concatenated PXIe-2535 modules of 136 output columns each. This allows us to connect each of the four channels of the DMM under software control to any of the 9×136=1,224 SMX output columns. Figure 6 shows that the system supports two-point and four-point (Kelvin) resistance measurements between any pair of probe tips (for daisy chains) as well as between a single probe tip and all other probe tips ganged (for characterization of that single probe tip when all probe tips are shorted through the probed wafer).
Results and Conclusion
On 300 mm test wafers (which we designed and manufactured in-house and contain microbumps with various metallurgies, pitches, diameters, and sizes), we successfully demonstrated the following:
All WIO1 probe tips do land on the corresponding microbumps (see Figure 7).
The actual contact resistance between probe tip and microbump is Rc ~ 0.1 Ohm. However, the resistance of the trace through the thin film membrane on the probe core is often included in the measurement: Rc ~ 5 Ohm (see Figure 8).
Probe marks on Cu are small, while probe marks on Sn are larger, but can be removed through reflow. We demonstrated experimentally that there were no stacking interconnect yield differences between all four cases of bottom/top microbumps probed/not-probed [5].
Through cost modeling, we demonstrated that, for single-site testing, the Pyramid® Probe cards, although expensive, financially outperform pre-bond testing through dedicated probe pads [5].
Original Authors:
Ferenc Fodor, IMEC
Edited by Cyth Systems
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