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Original Authors: Francis RAGUIN, Barco Silex
Edited by Cyth Systems
The Challenge
Performing the physical verification of an FPGA device by reusing its virtual simulation environment, following a DO 254 Level A methodology flow (Guidance document for the development of hardware components for airborne equipment).
The Solution
Designing a test system using an NI PXIe-1073 chassis with two NI PXIe-7962R FlexRIO boards coupled with two NI 6581 modules and programming the FPGA chips of the FlexRIO boards using the LabVIEW FPGA Module to integrate the constitutive elements of the virtual test bench.
Subsidiary of Barco Group, Barco Silex is an electronics design company that specializes in hardware developments (ASIC, FPGA, and embedded boards) and offers a wide range of IP core products for video and security applications. We have expertise and over 10 years of experience in ASIC and FPGA development under DO-254 guidance for prestigious clients such as Airbus, Safran, and Thales.
The NI test set consists of an NI PXIe-1073 chassis with two NI PXIe-7962R modules combined with two NI 6581 adapters. With an acquisition frequency up to 100 MHz, they allow monitoring of various FPGA input and output signals.
The usual approach to verify electronic components and ensure proper functional behavior is to use simulation tools. This type of verification allows testing an FPGA from its register-transfer level (RTL) (architecture description) representation as well as at the logic-gate level by incorporating the timing and gate delay notions.
The verification is then based on timing models of the constitutive elements of an FPGA (logic gates, phase-locked loops, memories, and so on).
However, the device behavior must also be silicon-proven to meet the DO-254 Level A expectations. Therefore, we developed a test bench based on NI equipment and a custom-printed circuit board to replicate the virtual verification environment at the physical level, while taking advantage of existing simulations.
A Unique Test Procedure
Using Perl-based software, the virtual test bench decodes the test procedures described by means of instructions to control both a test engine and the interfaces of the component to verify. LabVIEW can call this Perl program and allows the use of the same test vectors as those used on the virtual test bench. Therefore, the procedures set made and validated for FPGA simulations can be used directly on the physical test bench.
A Shared Architecture
The test engine architecture we developed and validated, as well as the interfaces of the component under verification, are written in VHDL language and can be interpreted by the simulator. The specification and design of this test environment are constrained by the portability between the simulator and the NI framework. The FlexRIO boards can therefore use this VHDL code to produce a physical test environment identical to the virtual one. Thanks to LabVIEW FPGA, we were able to integrate this code without any change while adding the necessary interfaces to handle the data exchange between the PXI bus and test PC.
The execution of all the FPGA verification procedures: 64.5 hours via logic-gate level simulations versus two hours via physical tests. The time saved is around a factor of 30.
The virtual test bench and the physical test bench both allow the same inputs and generate the same type of output data. The test procedures can hence be written for both.
Flexible Tools
In this way, we could combine three kinds of hardware description of the FlexRIO boards: (1) the use of IP integrated inside LabVIEW FPGA, (2) the VHDL code generation from the GUI of LabVIEW FPGA, and (3) the integration of the VHDL code complying with our quality standards. It allows the user to make the best out of each of these three solutions and integrate all of them into the same environment.
Original Authors:
Francis RAGUIN, Barco Silex
Edited by Cyth Systems
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